Title

Description

Idea by

This project involves the simulation of long on-chip interconnects used for point-to-point communication. The interconnect delay increases quadratically with the increase in its length. Uniform repeater insertion is one of the ways to make the quadratic dependence into linear with respect to line length.

Modeling Requirements:

1. Select higher level metal line of a chip (Metal 3 and higher) for obtaining the model.
2. Consider line length of 3mm-10mm for different simulation.
3. Model the interconnect as pi-3 or pi-5 distributed model for accuracy rather than lumped RC model. You can compare the difference in the delay for these two models for same line length using simulation.
4. Uniform Repeater insertion involves breaking the long line and make the quadratic dependence to linear.

N.B: Interconnect is one of the hottest problem in high-speed design. Lot of research is underway to improve speed and reduce power consumption.

This project can be started by students in
a group of 2-3.

Tools Recommended:

To begin with study the basics from Chapter 8 in J. Rabaey book (the reference is given below).
The interconnect and MOS model can be obtained from UC, Berkeley website at: http://www-device.eecs.berkeley.edu/~ptm/interconnect.html

Reference: 1. J. M. Rabaey, "Digital Integrated Circuits", Wiley Eastern Publications, 1996.

I can provide with many more references, when the project begins.

This project implements a low-power Static Random Access Memory (SRAM) in CMOS.

The top level specs are:
- 8 bit Address
- 16 bit Data In
- 16 bit Data Out
- Chip Select input to enable the SRAM chip
- Output Enable input to enable the tri-stated data out pins
- Write Enable input to differentiate read and write operations
- Total capacity = 2^8 x 16 = 4096 bits = 4 Kb
- Internal Architecture (Flexible): An array of 64x64 bits

Description: 8 bit address is divided into two parts 6 bits for row decoder (to generate 64 Wordlines) and 2 bits for column decoder (to select one out of four 16 bit data out). One of the efficient implementation of the row decoder can be two-stage decoder. The wordlines can be pulse based instead of voltage level (for low power operation). The design can be synchronous (with clock) or asynchronous (without clock).
 

Design Tasks: Background Study for SRAM, CMOS circuit styles, Design, Analysis, Pre-layout simulation, Layout, Verification (DRC and LVS), Parasitic extraction, Post-layout simulation, Documentation

Tools Recommended:

Recommended Books:

(1.) Jan M. Rabaey*, "Digital Integrated Circuits: A Design Perspective", Prentice Hall, NJ, 1996. (Online Material First Edition and Second Edition)
(2.) Ken Martin*, "Digital Integrated Circuit Design", Oxford University Press, NY, 2002.
(3.) Neil H. E. Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design: A System Perspective", Addison-Wesley, 1993.

Online Documents:

(1.) Bharadwaj S. Amrutur, "Design and Analysis of Fast Low Power SRAMs," Ph.D. Thesis, Stanford University, CA, 1999.
(2.) Mark A. Horowitz, "Timing Models for MOS Circuits," Ph.D. Thesis, Stanford University, CA, 1984.
(3.) Other miscellaneous publications from Stanford University, CA.

CAD Tools needed:
Simulation and Layout: Cadence.
Simulation (optional): SPICE/Any circuit simulator that can simulate MOS circuits.
Layout (optional): Magic/IC Editor/Any layout tool.

Duration: 3-6 months for a group of 2-3 3rd/4th year B.Tech. students

* We have shipped two copies of each book (Rabaey, and Martin) to the department. If interested, please check the departmental library to have a reading.