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Excellent White Papers from Cadence

URL: http://www.cadence.com/whitepapers

CONTENTS:

Download: Useful Resources from Intel

Open Source Software contains libraries, tools and test suits, operating systems, compilers, drivers, and platforms.
Research Library contains research publications in PDF. The documents can be browsed topicwise.

POWER3: The next generation of PowerPC processors
by F. P. O'Connell and S. W. White, IBM Enterprise Server Group, Austin, Texas

The POWER3 processor is a high-performance microprocessor which excels at technical computing. Designed by IBM and deployed in various IBM RS/6000® systems, the superscalar RISC POWER3 processor boasts many advanced features which give it exceptional performance on challenging applications from the workstation to the supercomputer level. In this paper, we describe the microarchitectural features of the POWER3 processor, particularly those which are unique or significant to the performance of the chip, such as the data prefetch engine, nonblocking and interleaved data cache, and dual multiply–add-fused floating-point execution units. Additionally, the performance of specific instruction sequences and kernels is described to quantify and further illuminate the performance attributes of the POWER3 processor.
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IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology
by B. W. Curran, Y. H. Chan, P. T. Wu, P. J. Camporese, G. A. Northrop, R. F. Hatch, L. B. Lacey, J. P. Eckhardt, D. T. Hui, and H. H. Smith

The IBM eServer z900 microprocessor is a seventh-generation zSeries™ (formerly S/390®) CMOS design which has achieved 1.3-GHz operation. This paper describes the 0.18-µm bulk CMOS, seven-level copper metal process and the high-frequency circuit, integration, and design methodologies developed to achieve this operation. The microprocessor was floorplanned to closely mimic the flow of the microarchitecture pipeline and reduce the communication delay overhead between units. Novel circuit techniques were used in the implementation of the arrays and cache hit detection logic to save power and reduce circuit complexity without sacrificing performance. A four-dimensional gate library and novel synthesis algorithms were developed to yield synthesized control implementations with the performance characteristics of a fully custom circuit design.
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Advanced microprocessor test strategy and methodology
by W. V. Huott, T. J. Koprowski, B. J. Robbins, M. P. Kusko, S. V. Pateras, D. E. Hoffman, T. G. McNamara, and T. J. Snethen

This paper describes the overall test methodology used in implementing the S/390® microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test patterns and in measuring test effectiveness. Microprocessor advances in architectural complexity, circuit density, cycle time, and technology-related issues, coupled with IBM's high requirements for quality, reliability, and diagnosability, have made it necessary to develop testing methods and attain quality levels that far exceed what others have approached.
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Intel CTO says chip design needs rethinking
Peter Clarke
06/08/2004 7:41 PM EST
URL: http://www.siliconstrategies.com/article/showArticle.jhtml?articleId=21402321

SAN DIEGO, Calif. -- Tools and methodologies need to be "fundamentally reconsidered" as the electronics world enters an era of unprecedented complexity, the chief technologist of Intel Corp. said Tuesday (June 8).

Pat Gelsinger, delivering the keynote at the 41st Design Automation Conference here, outlined the many challenges facing designers in the coming years, from gate and source-drain leakage problems to vexing variability issues which cannot be managed by contemporary tools.

"We believe our design methodologies and our design tools need to be fundamentally reconsidered," Gelsinger said.

Gelsinger struck notes of hopefulness amid the description of major potholes in the design landscape, saying one should "fundamentally believe in (Moore's) the law." He described the Semiconductor Industry Association's road map as "promising."

"We believe this doubling remains possible and we're confident it's something we can deliver against," he said. The 486 microprocessor, which Gelsinger oversaw, was 1.12 million transistors and the next Itanium will be north of 1 billion, he noted.

However, the issues of power dissipation and process and on-chip variations are thorny ones that require new ways of thinking, he said. While gate oxide thinness should be solved with high-k dielectrics, the problems of source-drain leakage are increasing exponentially, Gelsinger said. To deal with it, Intel is looking at tri-gate structures to mitigate leakage.

Variation, however, represents "a new class of challenges on horizon that changes everything about our industry," he noted.

With static variation, for instance, "I have a distribution of devices, some leaky, some less, some faster than others," Gelsinger said. With dynamic variations, designers run into local hot spots and variations chip. As process rules shrink, fewer atoms end up on the channel and often designers get a non-uniform distribution of those atoms, another variation issue.

"Everything we do in our designs will have a probabilistic element to it," he said.

Using the Pentium 4 Northwood processor as an example, Gelsinger said Intel has good control on frequency variation, around 30 percent at 130nm design rules. However, leakage power ranges from five to 10 times.

"Our tools don't need to optimize for speed or logic functionality. They need to consider yield and bit splits, parameters and variations, leakage power, the distribution of that across the die, "Gelsinger said. "We need design tools and environments that integrate all these variables together."

Microprocessors of Past and Present
An comprehensive source of information on the Microprocessors of the Past and Present:
http://www.cs.uregina.ca/~bayko/cpu.html

P6 Family of Processors
For getting to know about the architecture about the P6 family of processors and the 32 bit Pentium microprocessors check out this link to get your free intel manuals. These are helpful for the 3rd year course in Microprocessors and very helpful for people who want to try their hand in writing their own small Operating Systems for the 32 Pentium processors.

http://www.intel.com/design/pentium4/manuals/253665.htm